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Equivalence checking of a floating-point unit against a high-level C model

Abstract:

Semiconductor companies have increasingly adopted a methodology that starts with a system-level design specification in C/C++/SystemC. This model is extensively simulated to ensure correct functionality and performance. Later, a Register Transfer Level (RTL) implementation is created in Verilog, either manually by a designer or automatically by a high-level synthesis tool. It is essential to check that the C and Verilog programs are consistent. In this paper, we present a two-step approach, e...

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Publication status:
Published
Peer review status:
Peer reviewed

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Publisher copy:
10.1007/978-3-319-48989-6_33

Authors


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Institution:
University of Oxford
Oxford college:
Balliol College
Role:
Author
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Institution:
University of Oxford
Division:
MPLS
Department:
Computer Science
Role:
Author
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Institution:
University of Oxford
Division:
MPLS
Department:
Computer Science
Role:
Author
Publisher:
Springer Publisher's website
Journal:
21st International Symposium on Formal Methods Journal website
Volume:
9995 LNCS
Pages:
551-558
Host title:
21st International Symposium on Formal Methods
Publication date:
2016-11-01
Acceptance date:
2016-08-23
DOI:
ISSN:
0302-9743 and 1611-3349
Source identifiers:
664487
ISBN:
9783319489889
Pubs id:
pubs:664487
UUID:
uuid:3c37e9f9-2f8b-490e-8b52-711752269102
Local pid:
pubs:664487
Deposit date:
2017-01-28

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